【Location】Shanghai

【Responsibilities】

1.Working on complex digital design verification

2.Working closely with algorithm/system/software engineers performing in depth analysis/evaluation of software,analog, digital architectural partitioning trade-offs and other variable sensor system related factors.

3.Exercising good judgement in selecting methodologies, techniques and evaluation criteria

【Requriements】

1.Bachelor’s Degree in Electrical Engineering,and Master’s Degree in Electrical Engineering preferred

2.ASIC, SoC or FPGA design and/or verification and simulation on sub-system and/or chip level

3.Deep knowledge on ASIC/SoC design/verification methodologies

4.At least 3 years of related experience

5.Good software skills and some level of processor based verification

6.Fluent in Verilog/System Verilog

7.Embedded Software design and test

8.TCL/Python/Perl/etc.

9.Experience in Test bench design

10.IT Environment like Linux, GIT

11.Experience from verification in lab

12.Ability to write detailed and clear microarchitecture documentation

13.Ability to write detailed and clear verification plan documentation

14.Fluent in English speaking and writing

Additional desirable skills include:

1.Knowledge in System Verilog Assertions

2.Experiences in Formal verification

3.Knowledge about several standard interfaces, such as Ethernet, I2C, SPI, UART, CAN/CAN-FD, JTAG etc.