SoC Verification Intern
- Writing verification-related documents based on design manual and product definitions;
- Architecting IP verification environments and transplanting SoC environments;
- Analyzing coverage and completing verification closure;
- Doing pre- and post-synthesis simulation of IP modules and bug tracking;
- Supporting FPGA verification and chip testing.
- PhD or master students majoring in Communications Engineering, Electronics or Microelectronics;
- Solid basic knowledge of digital circuits;
- Knowledge of ASIC design process;
- Familiarity with Verilog and SystemVerilog;
- Familiarity with Linux and EDA preferred;
- Familiarity with Python and Perl preferred;
- Familiarity with UVM preferred;
- At least 3 days a week for 6 months or longer.