With the rapid evolution of autonomous driving, chips are more widely applied in vehicles. Due to demanding operating conditions, automotive chips throughout their lifecycles have to endure changing temperature and humidity conditions, electromagnetic interference from integrated circuits, as well as vibrations and impacts in the driving process. Therefore, an exceptionally high level of reliability and safety is required for automotive chips.

In response to high standards and stringent requirements on automotive chips, Calterah, as a leading player in the mmWave radar chip market, adheres to its core value of “Quality Pursuit” and its quality policy of “With a pledge of quality, we innovate for the greater good”. Recently, Calterah hosted its third “Quality Month” event spanning over a month, to raise quality awareness of all Calterah members and enhance its “Zero Defects” management of automotive-grade chips, thus facilitating innovations in quality management, and the delivery of mmWave radar technologies with higher quality, reliability, and performance.

J Lab Open Day: Explore World-Leading mmWave RF Testing Solutions

Calterah boasts a 5S Class 10,000 clean laboratory with Electrostatic Discharge (ESD) protection, J Lab. Calterah’s proprietary high-frequency SoC testing solutions developed with J Lab are capable of ensuring that automotive-grade SoCs can meet the extremely demanding operating conditions and the requirement of a longer lead time. In Calterah, each automotive-grade chip undergoes rigorous tri-temperature tests against thousands of items to ensure a 100% testing rate. That is to say, every chip delivered to our customers is fully tested, with well-assured quality.

In this year’s “Quality Month” event, employees from various departments visited Calterah’s ATE laboratory, J Lab and explored the automatic test equipment as well as other testing facilities, thus gaining a full picture of how to perform the ATE testing on automotive-grade mmWave radar chips. After the visit, a member of the R&D team said, "Through this event, we have gained profound insights into the entire process of chip testing. Moreover, we become more aware that stringent design assurances for quality and related testing items are necessary for improving production efficiency and yield.”

Lectures on Quality Management and Control Help to Drive Innovative Chip Design

During the “Quality Month”, Calterah held three lectures on FA, DFMEA, and ASPICE application respectively to emphasize its commitment to excellent quality and inspire continuous innovations in chip design.

Lecture on FA: Failure analysis (FA) is a necessary technology for various phases in the chip lifecycle, such as chip design, reliability testing, yield improvement, and return material authorization (RMA). Fully aware of the critical role of FA in quality assurance, Calterah attaches great importance to building FA capabilities. In the lecture, Calterah’s FA expert addressed issues most frequently encountered by Calterah staff, such as the initiation of an FA process, common failure modes and mechanisms, equipment for failure analysis and its principles, case study, etc., thus providing an overview on this powerful analysis tool. Through failure analysis, Calterah constantly iterates the chip design and optimizes production to improve the quality and reliability of chips.

Lecture on DFMEA: Design failure mode and effects analysis (DFMEA), as an internationally recognized tool for product quality control during the design phase, analyzes potential failure modes and their effects, playing a pivotal role in quality enhancement of chip design. Considering DFMEA an indispensable part in the “Zero Defects” management, Calterah integrates quality management into the entire lifecycle of its products from design to production, to guarantee higher quality, reliability, and performance of high-frequency mmWave technologies. After learning about DFMEA fundamentals and the essentials of operation procedures during the lecture, employees have deepened their understanding of the significance of quality control during the design phase.

Lecture on ASPICE Application: Automotive Software Process Improvement and Capacity dEtermination (ASPICE) management, with the aim to establish and enhance the process of software quality management, helps to improve the compliance level of software development through standardization and constant workflow optimization. Recently, Calterah’s AUTOSAR project has achieved ASPICE CL2 (Capability Level 2), demonstrating a notable improvement in software quality management and its R&D quality system. With the pursuit of high quality, Calterah constantly aligns its R&D process to the ASPICE standard, adhering to regulations and norms in the automotive industry. Meanwhile, to provide customers with high-quality and competitive products, Calterah endeavors to improve the R&D process, efficiency, iteration capability, and reusability, reducing faults and failures to meet higher quality requirements. This comprehensive and systematic management framework has been thoroughly elucidated in the lecture, inspiring employees to strive for continuous innovations in process design and improvements.

By hosting the “Quality Month” event, Calterah emphasizes its unremitting pursuit of high quality among employees and inspires innovations in chip design and testing processes, thus laying a solid foundation for future technological innovations, R&D, and mass production of products. Upholding the core value of “Quality Pursuit”, Calterah has adhered to “Zero Defects” management thoroughly to improve chip quality, delivering on its quality policy of “With a pledge of quality, we innovate for the greater good”.